1. Field of the Invention
This invention generally relates to predicting the address of the next instruction to fetch after a branch or jump instruction is fetched, and more particularly to predicting the address of the next instruction to fetch after a jump instruction has been fetched where the jump instruction is preceded by a skip instruction.
2. Background
Prediction mechanisms are used in computer systems to predict the address of the next instruction to fetch for execution when the present instruction is a BRANCH or JUMP instruction. For the remainder of this specification the JUMP instruction is used to connote both BRANCH and JUMP instructions. The objective of the prediction mechanism is to increase instruction processing throughput by having the next instruction to be executed available for processing before a condition in the JUMP instruction has been evaluated. Processor time may be saved by not having to wait for the next instruction to be fetched following execution of a JUMP instruction.
Generally speaking, the prediction made must be correct more often than not in order for the JUMP prediction to achieve its objective of achieving increased processor performance. This is because of the lost processing time associated with mispredicting the next instruction. If a misprediction occurs, the predicted instruction must be aborted and the correct instruction must be fetched. In a pipelined machine where a condition in a JUMP instruction is not evaluated until late in the pipeline, instructions following the predicted instruction may have been loaded and have to be aborted also.
To achieve a desired rate of correct predictions, JUMP prediction mechanisms rely on the principle that a JUMP instruction is likely be evaluated the same as its most recent executions, and therefore the instruction to follow the JUMP instruction is predicted to be the same as in recent executions.